1. Field of the Invention
The present invention relates to a drive circuit and a method for driving a flat panel display device, and in particular, to these suitable for use in a plasma display device.
2. Description of the Related Art
Conventionally, there are two-electrode type plasma display panels (PDPs) which perform selective discharge (address discharge) and a sustain discharge between two electrodes, and three-electrode type PDPs performing address discharge using the third electrode as plasma display devices such as AC drive type PDPs, which are one of matrix type flat panel display devices. Further, in the three-electrode type, the third electrode can be formed on a substrate on which a first electrode and a second electrode performing the sustain discharge are disposed, or the third electrode can be formed on the other opposing substrate.
Since any of the above-described respective type PDP devices have the same operational principle, a configuration example of the PDP device in which the first and second electrodes performing sustain discharge are provided on the first substrate and at the same time, aside from this, the third electrode is provided on the second substrate opposing the first substrate will be explained hereinafter.
FIG. 12 is a view showing an entire configuration of the AC drive type PDP device.
In FIG. 12, the AC drive type PDP device 1 is provided with scanning electrodes Y1 to Yn parallel to each other and common electrodes X on the first substrate, and at the same time, address electrodes A1 to Am are provided on the second substrate opposing to the first substrate in the direction perpendicular to these electrodes Y1 to Yn, and X. The common electrodes X are provided in correspondence with the respective scanning electrodes Y1 to Yn close to these, and the electrodes are connected to each other at one end in common.
A display panel P of the AC drive type PDP device 1 is provided with a plurality of cells disposed in a two-dimensional matrix of m columns and n rows. Each cell Cij is formed by an intersection point of an scanning electrode Yi and an address electrode Aj, and the common electrode X adjacent in correspondence with the intersection point. This cell Cij corresponds to a pixel of a display image, so that the display panel P can display a two-dimensional image.
A common end of the common electrodes X is connected to an output end of an X-side circuit 2, and the respective scanning electrodes Y1 to Yn are connected to output ends of a Y-side circuit 3. The address electrodes A1 to Am are connected to output ends of an address side circuit 4. The X-side circuit 2 is composed of a circuit to repeat discharging, and the Y-side circuit 3 is composed of a circuit to scan linear sequentially and a circuit to repeat discharge. The address side circuit 4 is composed of a circuit to select rows to be displayed.
The X-side circuit 2, the Y-side circuit 3 and the address side circuit 4 are controlled by control signals supplied from a control circuit 5. In other words, display operation of the PDP device is performed by determining a cell to be lit with a circuit scanning linear sequentially in the Y-side circuit 3 and the address side circuit 4, and repeating discharge with the X-side circuit 2 and the Y-side circuit 3.
The control circuit 5 generates the control signals based on display data D, a clock CLK indicating a timing at which the display data D is read, a flat panel synchronizing signal HS, and a vertical synchronizing signal VS which are supplied from outside, and supplies these control signals to the X-side circuit 2, the Y-side circuit 3, and the address side circuit 4.
FIG. 13A is a view showing a cross sectional configuration of a cell Cij in column i, row j, which is a pixel. In FIG. 13A, the common electrode X and the scanning electrode Yi are formed on a front glass substrate 11. A dielectric layer 12 to insulate from a discharge space 17 is coated over these electrodes and further over it, an MgO (magnesium oxide) protection film 13 is coated.
Meanwhile, the address electrode Aj is formed on a rear glass substrate 14 disposed facing to the front glass substrate 11. A dielectric layer 15 is coated over it and phosphor 18 is coated further over it. Ne+Xe Penning gas or the like is filled in the discharge space 17 between the MgO protection film 13 and the dielectric layer 15.
FIG. 13B is a view for explaining a capacity Cp of the AC drive type PDP device. As shown in FIG. 13B, in respective cells of the AC drive type PDP device, capacity components Ca, Cb and Cc exist in the discharge space 17, between the common electrode X and the scanning electrode Yi, and the front glass substrate 11 respectively, and the capacity Cpcell per one cell is determined according to the total of these capacity components (Cp cell=Ca+Cb+Cc). The total sum of the capacity of all cells is the panel capacity Cp.
FIG. 13C is a view for explaining luminescence of the AC drive type PDP device. As shown in FIG. 13C, the phosphor 18 in red, blue and green is put in order and coated inside a rib 16 in a strip-shape so that the phosphor 18 is excited and emits light by discharging between the common electrode X and the scanning electrode Yi.
As described above, in the AC drive type PDP device, since discharging (sustain discharge) is performed between the common electrode X and the scanning electrode Yi in a cell to emit light, the X-side circuit 2 and the Y-side circuit 3 (hereinafter referred to as “drive circuit” also) serve as circuits to output a high voltage signal to discharge in the cell. Accordingly, respective elements composing the drive circuit are required a high withstand voltage, which results in a factor to push up the manufacturing cost of the AC drive type PDP device. Therefore, a technology to lower the withstand voltage of the respective elements composing the drive circuit to realize reduction of the manufacturing cost is proposed. For instance, a drive circuit to perform discharge between electrodes by applying positive voltage to one electrode and negative voltage to the other electrode to create potential difference between electrodes to cause discharge is proposed (see Patent Document 1, and Non-Patent Document 1).
FIG. 14 is a view showing a configuration of the drive circuit in the AC drive type PDP device disclosed the Patent Document 1.
In FIG. 14, a capacitive load (hereinafter, referred to as “load”) 20 is the total sum of capacity of each cell formed between a common electrode X and a scanning electrode Y. In the load 20, the common electrode X and the scanning electrode Y are formed. Here, the scanning electrode Y is an arbitrary scanning electrode among a plurality of scanning electrodes Y1 to Yn.
The Y-side circuit 3 to drive the scanning electrode Y includes a power supply circuit 22 and a drive circuit 21.
The power supply circuit 22 includes a capacitor CY1, three switches SWY1, SWY2 and SWY3. The switches SWY1 and SWY2 are connected in series between a power supply line of a voltage Vs supplied from the power source and a ground (GND), which is a reference potential. One terminal of the capacitor CY1 is connected to an interconnection point between two switches SWY1 and SWY2, and the switch SWY3 is connected between the other terminal of the capacitor CY1 and the ground. Note that a signal line connected to the one terminal of the capacitor CY1 is referred to as a first signal line OUTAY, and a signal line connected to the other terminal is referred to as a second signal line OUTBY.
The drive circuit 21 includes two switches SWY4 and SWY5. The switches SWY4 and SWY5 are connected in series to both ends of the capacitor CY1 of the power supply circuit 22. In other words, the switches SWY4 and SWY5 are connected in series between the first and second signal lines OUTAY, OUTBY. The interconnection point of two switches SWY4 and SWY5 is connected to the scanning electrode Y of the load 20 via an output line OUTCY.
The X-side circuit 2 for driving the common electrode X includes a power supply circuit 24 and a drive circuit 23. The power supply circuit 24 and the drive circuit 23 correspond to the power supply circuit 22 and the drive circuit 21 in the Y-side circuit 3 respectively. Since the configuration thereof is similar to that of the power supply circuit 22 and the drive circuit 21, respectively, explanation will be restrained.
On the Y side of the drive circuit shown in FIG. 14, by turning the switches SWY1, SWY3 and SWY4 on and the switches SWY2 and SWY5 off, an electric charge in accordance with the voltage Vs given by the switches SWY 1 and SWY3 is stored in the capacitor CY1 and the voltage Vs of the first signal line OUTAY is applied to the load 20 via the output line OUTCY.
Further, in a state that the electric charge in accordance with the voltage Vs is stored in the capacitor CY1, by turning the switches SWY2 and SWY5 on, and switches SWY1, SWY3 and SWY4 off, a voltage of the second signal line OUTBY becomes (−Vs) and the voltage (−Vs) is applied to the load 20 via the output line OUTCY.
Thus, a positive voltage Vs and a negative voltage (−Vs) are alternately applied to the scanning electrode Y of the load 20. Similarly, by performing similar switching control to the common electrode X of the load 20, the positive voltage Vs and the negative voltage (−Vs) are alternately applied. At this time, the voltages (±Vs) applied to the scanning electrode Y and the common electrode X are controlled in such a manner that their phases are in an opposite relation to each other. In other words, when a positive voltage Vs is applied to the scanning electrode Y, a negative voltage (−Vs) is applied to the common electrode X, thereby enabling the creation of a potential difference which makes a discharge between the scanning electrode Y and the common electrode X possible.
FIG. 15 is a waveform diagram showing an operation of the AC drive type PDP device shown in FIG. 12. FIG. 15 shows a waveform example of a voltage applied to the common electrode X, the scanning electrode Y and the address electrode for a sub-field among a-plurality of sub-fields constituting one frame. One sub-field is divided into a reset period composed of an entire writing period and entire erasing period, and an address period and a sustain discharge period.
In the reset period, first, the voltage applied to the common electrode X is reduced from the ground potential level, reference potential, to (−Vs). On the other hand, the voltage applied to the scanning electrode Y is gradually increased with time, and a final voltage obtained by combining the writing voltage Vw and the voltage Vs is applied to the scanning electrode Y.
Thus the potential difference between the common electrode X and the scanning electrode Y becomes (2 Vs+Vw), in spite of being still in a display state as before, discharge is performed in all cells of whole display lines, so that a wall electric charge is formed.(entire writing).
Next, after the voltage of the scanning electrode Y is returned to Vs, the voltage to the common electrode X is increased from (−Vs) to Vs, and at the same time an impressed voltage to the scanning electrode Y is reduced to (−Vs). Thereby, a discharge is started because the voltage of the wall electric charge itself exceeds the discharge start voltage over all cells, so that the stored wall electric charge is erased (entire erasing).
Next, during the address period, in order to perform ON/OFF of the respective cells according to display data, the address discharge is performed linear sequentially. At this time, the voltage Vs is applied to the common electrode X. When a voltage is applied to the scanning electrode Y corresponding to a certain display line, a scan pulse at (−Vs) level is applied to the scanning electrode Y selected linear sequentially, and the voltage at a ground potential level is applied to a not-selected scanning electrode Y.
At this time, an address pulse at a voltage Va is selectively applied to an address electrode Aj corresponding to a cell causing the sustain discharge, that is a cell to be lit, among respective address electrodes Al to Am. As a result, discharge is taken place between the address electrode Aj of the cell to be lit and the scanning electrode Y selected linear sequentially, and a certain amount of the wall electric charge required for next sustain discharge is stored on an MgO protection film surface over the common electrode X and the scanning electrode Y, using the above discharge as a priming (pilot flame).
It should be noted that though FIG. 15 shows an example in which the address period is divided into a first half address period (for instance, sequential scan pulses are applied to the scanning electrodes Y in odd-numbered lines) and the second half address period (for instance, sequential scan pulses are applied to the scanning electrodes Y in even-numbered lines), it is also acceptable to apply the sequential scan pulse to the scanning electrode Y without dividing the address period.
Thereafter, during the sustain discharge period, sustain discharge is performed by alternately applying voltages (+Vs and −Vs) different in polarity from each other to the common electrodes X and the scanning electrodes Y of respective display lines by the drive circuit shown in FIG. 14, and an image of one sub-field is displayed. Incidentally, an operation of alternately applying voltages different in polarity from each other is called a sustain operation, and a pulse at the voltages (+Vs and −Vs) during the sustain operation is called a sustain pulse.
Note that the voltage (Vs+Vx) is applied only when a high voltage is applied first to the scanning electrode Y during the sustain discharge period. This voltage Vx is that to be added for generating a voltage necessary to the sustain discharge by adding to the voltage of the wall electric charge generated during the address period.
(Patent Document 1)
Japanese Patent Application Laid-open No. 2002-62844
(non-Patent Document 1)
“A new Driving Technology for PDPs with Cost Effective Sustain Circuit”, SID 01 DIGEST, pp. 1236 to pp. 1239, in 2001, Kishi et al.
Here, in the drive circuit shown in FIG. 14, only three electric potentials, ie. Vs, ground potential level and (−Vs) can be applied to the load 20. However, when the AC drive type PDP device 1 shown in FIG. 12 is operated, the use of a potential larger in potential difference than the potential Vs and (−Vs) is sometimes required for the ground potential level which is a reference potential.
For instance, when address discharge is performed during the address period, the larger the potential difference between the voltage (−Vs) of the scan pulse and the voltage Va of the address pulse, the more the voltage margin related to the scan pulse is increased, so that a stable address discharge can be performed. However, since the range capable of increasing the voltage Va of the address pulse is limited, it is required to set the voltage of the scan pulse lower, in order to make the potential difference between the voltage of the scan pulse and that of the address pulse large.
As a method of lowering the voltage of the scan pulse, as shown in FIG. 16, a drive circuit is conceivable, which is configured to directly apply a voltage (−Vy′) lower than the voltage (−Vs) to the load 20. Incidentally, in FIG. 16, only the Y-side circuit is shown and the same symbols and numerals are attached to the components having the same functions as those of the components shown in FIG. 14.
In FIG. 16, a numeral 25 designates a negative potential supply circuit. The negative potential supply circuit 25 includes a switch SWY11 connected between a power supply line of the voltage (−Vy′) supplied from the power source and the output line OUTCY. By configuring like this and controlling the switch SWY11, it becomes possible to apply the voltage (−Vy′) which is lower than (−Vs) to the load 20.
However, in the drive circuit shown in FIG. 16, there is a problem in that a negative potential must be supplied to every output end (output line OUTCY) for the load 20. Furthermore, since a voltage of (Vs+Vy′) is exerted on the switch SWY4 in the drive circuit 21 and the switch SWY11 in the negative potential supply circuit 25, material for the switches SWY4 and SWY11 must be high in withstand voltage leading to increased manufacturing costs.